FIG. 1 illustrates a conventional imager 100 in block diagram form. As illustrated, the imager 100 includes a power source 110, a pixel array 120 including a plurality of pixels 121, a plurality of load circuits 130, a plurality of sample and hold circuits 140, and a plurality of amplifiers 150. Typically, there are numerous pixels 121 arranged in a plurality of rows and columns. However, for simplicity, the pixel array 120 illustrated in FIG. 1 only includes two columns and one row of pixels 121. The power source 110 produces a bias current IBIAS at an array pixel voltage of VAAPIX. Load circuit 130 produces a bias current IBIAS and this bias current IBIAS is supplied to each pixel 121 of the imager 100. The imager 100 also includes a control circuit 160 for generating the illustrated control signals (e.g., ROW, TX, RESET, SHR, SHS, and OUT) and additional image processing circuitry 170 for further processing signals output by the pixels 121.
Now also referring to FIGS. 2-5, the operation of the imager 100 is explained. FIG. 2 illustrates a conventional four transistor pixel 121. The pixel 121 includes a photodiode 122, a transfer transistor 123, a reset transistor 124, a source follower transistor 125, and a row select transistor 126. The pixel 121 accepts the ROW control signal at node F1 (coupled to the gate of the row select transistor 126), the TX control signal at node D1 (coupled to the gate of the transfer transistor 123) and the RESET control signal at node C1 (coupled to the gate of the reset transistor 124). The pixel 121 accepts at node A1 power from an output node (e.g., nodes B01 or B02) of the power source 110 and produces reset “Vrst” and photo “Vsig” signals as outputs at node B1. As described in greater detail below, the pixel 121 also includes a charge detection node E1.
Now also referring to the timing diagram of FIG. 5, it can be seen that initially (i.e., at time t0), control signals ROW, RESET, TX, SHR, and SHS are not asserted (i.e., at a logical low level).
At time t1, the ROW control signal is asserted and supplied to node F1 to activate row select transistor 126.
At time t2, the RESET control signal is asserted, causing voltage VAAPIX supplied from the power supply 110 at node A1 to be applied to the charge detection node E1. Since node E1 is coupled to the gate of transistor 125 and node F1 is coupled to the gate of transistor 126, both transistors 125 and 126 conduct. As a result, the reset signal Vrst is output at node B1.
At time t3, the control signal RESET is deasserted and the charge detection node E1 becomes floating. The photodiode 122 has already accumulated charge at node P1 while it has been exposed to light since the last initialization. This exposure period is also known as an integration period.
At time t5, the control signal TX is asserted, causing charge transfer from the node P1 to the charge detection node E1. As a result, this charge is dumped to node E1. This charge decreases the voltage at node E1, and affects the conductivity of the source follower transistor 125. Since row select transistor 126 is still conducting, a photo signal Vsig based on the transferred charge at node E1 is output at node B1. In FIG. 5, the variability of the photo signal Vsig at node B1 is illustrated by three traces 511, 512, 513. The top trace 511 indicates the output at B1 if the photodiode 122 was exposed to little if any light during the integration period. The middle trace 512 corresponds to moderate light exposure during the integration period. The bottom trade 513 corresponds to strong light exposure during the integration period.
At time t8, the ROW control signal is deasserted, causing the row select transistor 126 to become non-conducting. As a result, the output at node B1 is shut off.
The pixel 121 therefore produces two output signals, namely a reset signal Vrst and a photo signal Vsig. The two signals Vrst and Vsig are produced at different times, but both signals are output at node B1. The outputs of the pixel 121 are routed to a load circuit 130, so that the source follower transistor 125 and the load circuit comprise a voltage follower circuit when the ROW control signal is asserted.
FIG. 3 illustrates the load circuit 130 used in the imager 100. The circuit 130 is a current sink for the output of the pixel circuit 121. As illustrated, the load circuit 130 accepts the output signals Vrst, Vsig of the pixel 121 at node A2 and produces corresponding outputs at node B2. The output of the load circuit 130 is generically referred to as Vpixout, which corresponds to a modified form of the reset signal between times t3 and t5 and corresponds to a modified form of the photo signal between times t5 and t8. The transistor 131 has its gate coupled to node C2, which accepts a control signal VLN. The control signal VLN is used to adjust the bias current generated by the transistor 131 and for optimizing the performance of the source follower circuit with regard to power consumption and speed. This transistor 131 is often referred to as a biasing transistor.
FIG. 4 is a circuit diagram of the sample and hold circuit 140. The function of the sample and hold circuit 140 is to sample and hold the reset and photo signals Vrst, Vsig of pixel 121 and output a corresponding differential signal. The differential signal output by the sample and hold circuit 140 has as its components the reset signal Vrst (at node B31) and the photo signal Vsig (at node B32). The operation of the sample and hold circuit 140 is described below.
At time t3 (FIG. 5), the sample and hold circuit 140 accepts at node A3 the reset signal Vrst and the SHR control signal transitions from low to high. The OUT control signal and the SHS control signal are both low, so transistors 142, 145, and 146 are non-conducting while transistor 141 conducts. Accordingly, the reset signal Vrst charges capacitor 143, and is thus stored on capacitor 143.
At time t4 (FIG. 5), the SHR control signal transitions from high to low, causing transistor 141 to become non-conducting.
At time t5 (FIG. 5), the SHS control signal transitions from low to high. The OUT control signal and the SHR control signal are both low, so transistors 141, 145, and 146 are non-conducting while transistor 142 conducts. Accordingly, the photo signal Vsig charges capacitor 144, and is thus stored on capacitor 144.
At time t7 (FIG. 5) the SHS control signal transitions from high to low, causing transistor 142 to become non-conducting.
At time t8 (FIG. 5), the OUT control signal transitions from low to high, causing transistors 145 and 146 to conduct. Since the SHR and SHS control signals are both low, transistors 141 and 142 are non-conducting. Accordingly, charge from capacitors 143 and 144 begins to respectively and simultaneously flow to nodes B31 and B32 via transistors 145 and 146. For simplicity, the signal arising from charge flowing from capacitor 143 to node B31 is labeled as Vrst while the signal arising from charge flowing from capacitor 144 to node B32 is labeled as Vsig.
Now referring back to FIG. 1, it can be seen that the Vsig and Vrst signals, respectively output from nodes B31 and B32, are supplied to a differential amplifier 150, which produces a single ended output Vout. The Vout signal is representative of the output of a pixel 121 and can be supplied to the image processing circuit 170 for digitization, digital processing, and storage.
At time t9 (FIG. 5), the OUT control signal transitions from high to low, causing transistors 145 and 146 to stop conducting.
FIG. 6 is a block diagram of a conventional power source 110. As illustrated, the power source 110 includes a power source 111 which is coupled to a resistor 112. The resistor 112 represents the output resistance of the power source 111 and any parasitic components between the power source 112 and nodes B01 and B02. The circuit 110 outputs at nodes B01 and B02 a bias current IBIAS at a predetermined voltage VAAPIX.
One problem associated with the above described imager 100 is that when a pixel 121 is exposed to very bright light, the charge transferred from node P1 to node E1 can decrease the voltage at node E1 from the reset voltage (i.e., VAAPIX) to a ground voltage, causing the source follower transistor 125 to become non-conducting. This phenomenon is known as saturation. In an imager 100, pixel saturation causes a cut-off of the bias current. This results in a fluctuation in the voltage of the output signal at nodes B01, B02 of the power source 110. Since the power source 110 is coupled to multiple pixels 121, saturation of one or more pixels 121 can affect the output of other pixels 121. In particular, saturation of one or more pixels may manifest in the image produced by the imager 100 as unstable horizontal band-wise noise.
Another problem associated with the above described imager 100 occurs when extremely bright light, such as sunlight, is incident upon the pixel 121. This saturates the photodiode 122 by causing the photodiode to produce a very large current flow. This current flow can overflow through the transfer transistor 123 to the charge detection node E1. Additionally, the source junction of the reset transistor 124 also generates photo current between node E1 and the substrate, which causes the voltage at node E1 to drop off when the reset transistor is turned off. In fact, under such strong illumination conditions, the voltage at node E1 decreases after the reset transistor turns off at time t3 (FIG. 5), causing a drop in the level of the reset signal Vrst between time t3 and t4, which is stored in capacitor 143 when control signal SHR is deasserted at time t4 (FIG. 5). The photo signal Vsig is always saturated under such strong light conditions. That is, the photo signal Vsig is set to a minimum level near ground potential. The decrease in the reset signal Vrst level causes a reduction of the Vout signal since Vout is equal to Vsig-Vrst. Thus, a very bright light incident upon a pixel may result in a decrease in the output signal, which ultimately manifests as a negative photoconversion response. This phenomenon is also known as reverse video noise.
Accordingly, there is a need for a bias current supply circuit for use in an imager which is capable of producing a more stable pixel bias current independent of the amount of light incident upon the pixels of an imager. There is also a need for a bias current supply circuit which is resistant to reverse video noise when imaging extremely bright objects.